代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/403658/11513296
cpp nfd.cpp
#include
#include
#include
#include
#include
#include
using namespace std;
//-------------------------------------------------------------
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plg tc26id.plg
礦ision3 Build Log
Project:
E:\tc26soft\id\tc26ic.uv2
Project File Date: 12/12/2008
Output:
Build target 'Target 1'
assembling STARTUP.A51...
www.eeworm.com/read/403298/11519561
vhd sanjiaobo.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sanjiaobo IS
PORT(clk:IN STD_LOGIC;
outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
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vhd da_tran.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY da_tran IS
PORT(clk1:in STD_LOGIC;
rst:in std_logic;
qin:in std_logic_
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vhd sanjiaobo.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sanjiaobo IS
PORT(clk:IN STD_LOGIC;
outp: out STD_LOGIC_VECTOR(9 DOWNTO 0)
);
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vhd da_tran.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY da_tran IS
PORT(clk1:in STD_LOGIC;
cnt4:in std_logic;
rst:in std_logic
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vhd fp1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp1 IS
PORT(clk:IN STD_LOGIC;
outp: out STD_LOGIC
);
END fp1;
ARCHITECTURE rt
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vhd fp2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp2 IS
PORT(clk:IN STD_LOGIC;
outp: out STD_LOGIC
);
END fp2;
ARCHITECTURE rt
www.eeworm.com/read/403296/11519635
vhd chui.vhd
--捶 (等宽度等间隔的正负脉冲组输出，此脉冲比较规律)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity chui is
port(clk:in std_logic;
outp:out
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vhd rou.vhd
--揉 (脉冲组宽度由窄变宽，脉冲组的间隔不变),作用于较大肌肉群
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rou is
port(clk:in std_logic;
outp: