代码搜索：Parallel
找到约 6,530 项符合「Parallel」的源代码
代码结果 6,530
www.eeworm.com/read/350657/3121234
c bpck6.c
/*
backpack.c (c) 2001 Micro Solutions Inc.
Released under the terms of the GNU General Public license
backpack.c is a low-level protocol driver for the Micro Solutions
"BACKPACK" parallel port
www.eeworm.com/read/264095/4294962
c bpck6.c
/*
backpack.c (c) 2001 Micro Solutions Inc.
Released under the terms of the GNU General Public license
backpack.c is a low-level protocol driver for the Micro Solutions
"BACKPACK" parallel port
www.eeworm.com/read/161121/5558600
c bpck6.c
/*
backpack.c (c) 2001 Micro Solutions Inc.
Released under the terms of the GNU General Public license
backpack.c is a low-level protocol driver for the Micro Solutions
"BACKPACK" parallel port
www.eeworm.com/read/159825/5580890
h baycom.h
/*
* The Linux BAYCOM driver for the Baycom serial 1200 baud modem
* and the parallel 9600 baud modem
* (C) 1996 by Thomas Sailer, HB9JNX
*/
#ifndef _BAYCOM_H
#define _BAYCOM_H
#include
www.eeworm.com/read/393394/8290249
m dir2par.m
function [C,B,A] = dir2par(b,a);
% DIRECT-form to PARALLEL-form conversion
% --------------------------------------
% [C,B,A] = dir2par(b,a)
% C = Polynomial part when length(b) >= length(a)
%
www.eeworm.com/read/171074/9772418
m dir2par.m
function [C,B,A] = dir2par(b,a);
% DIRECT-form to PARALLEL-form conversion
% --------------------------------------
% [C,B,A] = dir2par(b,a)
% C = Polynomial part when length(b) >= length(a)
%
www.eeworm.com/read/415793/11053762
vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
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vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
www.eeworm.com/read/415793/11053844
vhd shiftlne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR
www.eeworm.com/read/415793/11053868
vhd shiftlne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR