代码搜索：Parallel
找到约 6,530 项符合「Parallel」的源代码
代码结果 6,530
www.eeworm.com/read/494555/6377504
h ppuser.h
/*
* User-space parallel port device driver (header file).
*
* Copyright (C) 1998-9 Tim Waugh
*
* This program is free software; you can redistribute it and/or
* modif
www.eeworm.com/read/493456/6393586
m dir2par.m
function [C,B,A] = dir2par(b,a);
% DIRECT-form to PARALLEL-form conversion
% --------------------------------------
% [C,B,A] = dir2par(b,a)
% C = Polynomial part when length(b) >= length(a)
%
www.eeworm.com/read/490168/6459908
m dir2par.m
function [C,B,A] = dir2par(b,a);
% DIRECT-form to PARALLEL-form conversion
% --------------------------------------
% [C,B,A] = dir2par(b,a)
% C = Polynomial part when length(b) >= length(a)
%
www.eeworm.com/read/484538/6579532
m ppspy_test.m
%
% beta parallel data spy implementation.
% USAGE: ppspy(A) spys the ddense object A
%
function ppspy(a)
[ecode,estr,mat_rows,mat_cols] = ppclient('ppsize',a);
if ecode ~= 0
error(estr);
end;
row
www.eeworm.com/read/264066/11330972
m dir2par.m
function [C,B,A] = dir2par(b,a);
% DIRECT-form to PARALLEL-form conversion
% --------------------------------------
% [C,B,A] = dir2par(b,a)
% C = Polynomial part when length(b) >= length(a)
%
www.eeworm.com/read/402219/11540432
h hwcfg.h
/* Define Parallel port register */
#define PORTADDRESS 0x378 /* Enter Your Port Address Here */
#define IRQ 7 /* IRQ Here */
#define DATAPORT PORTADDRESS + 0x00
#define STATUS
www.eeworm.com/read/342845/11996131
m dir2par.m
function [C,B,A] = dir2par(b,a);
% DIRECT-form to PARALLEL-form conversion
% --------------------------------------
% [C,B,A] = dir2par(b,a)
% C = Polynomial part when length(b) >= length(a)
%
www.eeworm.com/read/252132/12300499
vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
www.eeworm.com/read/252132/12300511
vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
www.eeworm.com/read/252132/12300598
vhd shiftlne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR