代码搜索：Parallel
找到约 6,530 项符合「Parallel」的源代码
代码结果 6,530
www.eeworm.com/read/350097/3130299
c daisy.c
/*
* IEEE 1284.3 Parallel port daisy chain and multiplexor code
*
* Copyright (C) 1999, 2000 Tim Waugh
*
* This program is free software; you can redistribute it and/
www.eeworm.com/read/350097/3130638
c lp.c
/*
* Generic parallel printer driver
*
* Copyright (C) 1992 by Jim Weigand and Linus Torvalds
* Copyright (C) 1992,1993 by Michael K. Johnson
* - Thanks much to Gunter Windau for pointing out to
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cpia readme.cpia
This is a driver for the CPiA PPC2 driven parallel connected
Camera. For example the Creative WebcamII is CPiA driven.
) [1]Peter Pregler, Linz 2000, published under the [2]GNU GPL
--------------
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readme
Parallel Mandelbrot in MPI
Written by Ed Karrels, karrels@mcs.anl.gov
This is a demo of the graphical tools built into MPE. It includes
rudimentary drawing routines and some simple mouse handling ro
www.eeworm.com/read/338256/3319080
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixii_lvds_tx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;
www.eeworm.com/read/338256/3319231
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixii_lvds_rx_parallel_reg is
generic(
channel_width : integer := 10
);
port(
clk : in vl_logic;
www.eeworm.com/read/337546/3334629
c pt.c
/*
pt.c (c) 1998 Grant R. Guenther
Under the terms of the GNU General Public License.
This is the high-level driver for parallel port
www.eeworm.com/read/328695/3437444
hier_info dds.hier_info
|dds
clock => SAdderSub:ParallelAdderSubtractor1i.clock
clock => SAdderSub:ParallelAdderSubtractori.clock
clock => AltiMult:Producti.clock
clock => SDelay:Delayi.clock
sclrp => SAdderSub:Parallel
www.eeworm.com/read/324920/3493444
c pt.c
/*
pt.c (c) 1998 Grant R. Guenther
Under the terms of the GNU General Public License.
This is the high-level driver for parallel port
www.eeworm.com/read/323894/3507333
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lvds_rx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;