代码搜索：Parallel
找到约 6,530 项符合「Parallel」的源代码
代码结果 6,530
www.eeworm.com/read/222058/14708900
h jtag.h
/*
* jtag.h : the head file for jtag.c
*
* This head file defines the connection between parallel port and JTAG.
* Wiggler is supported by defaul. If you want to support other interfaces,
www.eeworm.com/read/17631/744933
hier_info dds.hier_info
|dds
clock => SAdderSub:ParallelAdderSubtractor1i.clock
clock => SAdderSub:ParallelAdderSubtractori.clock
clock => AltiMult:Producti.clock
clock => SDelay:Delayi.clock
sclrp => SAdderSub:Parallel
www.eeworm.com/read/17746/755338
hier_info dds.hier_info
|dds
clock => SAdderSub:ParallelAdderSubtractor1i.clock
clock => SAdderSub:ParallelAdderSubtractori.clock
clock => AltiMult:Producti.clock
clock => SDelay:Delayi.clock
sclrp => SAdderSub:Parallel
www.eeworm.com/read/18434/788454
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lvds_tx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;
www.eeworm.com/read/18434/788511
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lvds_rx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;
www.eeworm.com/read/18434/789049
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lvds_tx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;
www.eeworm.com/read/18434/789124
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lvds_rx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;
www.eeworm.com/read/18434/789256
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lvds_rx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;
www.eeworm.com/read/18434/789328
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lvds_tx_parallel_register is
generic(
channel_width : integer := 4
);
port(
clk : in vl_logic;
www.eeworm.com/read/32279/880481
hier_info dds.hier_info
|dds
clock => SAdderSub:ParallelAdderSubtractor1i.clock
clock => SAdderSub:ParallelAdderSubtractori.clock
clock => AltiMult:Producti.clock
clock => SDelay:Delayi.clock
sclrp => SAdderSub:Parallel