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### uVision2 Project, (C) Keil Software ### Do not modify ! Target (Target 1), 0x0000 // Tools: 'MCS-51' Group (Source Group 1) File 1,2, 0x0 File 1,1,

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pwm is port(ctrl:in std_logic_vector(3 downto 0); ----PWM控制信号 clk:in std_logic; ------------1

Analysis & Synthesis report for pwm Fri Apr 07 20:52:37 2006 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Not

Assembler report for pwm Fri Apr 07 20:52:43 2006 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. A

|pwm clk => q[14].CLK clk => q[13].CLK clk => q[12].CLK clk => q[11].CLK clk => q[10].CLK clk => q[9].CLK clk => q[8].CLK clk => q[7].CLK clk => q[6].CLK clk => q[5].CLK clk => q[4].CLK cl

Timing Analyzer report for pwm Fri Apr 07 20:52:46 2006 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice

/* Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EPM7128SL84) Path("") File("pwm.pof")

module pwm(clock,keyin,pwm_out); input clock; input [1:0] keyin; output pwm_out; reg [20:0] count; reg [9:0] pwm_count; reg cnt_chg; reg pwm_reg; always @(posedge clock)

Flow Status : Successful - Fri Apr 07 20:52:40 2006 Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version Revision Name : pwm Top-level Entity Name : pwm Family : MAX7000S Device : EPM712

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY pwm IS PORT ( clk : IN STD_LOGIC; key : IN STD_LOGIC_VECTOR(1 DOWNTO