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PCB 的代码
进程调度模拟程序.txt
#define NULL 0
#include
#include
#include
#include
//定义一个pcb的结构体
FILE *GroupFile[10];
typedef struct index{
char name; //指令
cpu.cpp
#include "stdafx.h"
#include "all.h"
#include "Instruction.h"
#include "VM.h"
#include "CPU.h"
#include "PCB.h"
extern VM vm;
extern CString msg;
CPU::CPU()
{
Reset();
}
void CPU::Res
monitor.sts
#Allegro PCB Router V15.7 made 2006/05/31 at 22:07:34
#Host
#ROUTING STATUS >
Start Time: Report Time: Wed May 27 09:45:38 2009
Nets =
master.rul
DRC Rules Export File for PCB: E:\修改书稿\protel\09源文件\第六章\master.PcbDoc
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width|Scope=Board|Min
master.rul
DRC Rules Export File for PCB: E:\修改书稿\protel\09源文件\第六章\master\master.PcbDoc
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width|Scope=Bo
signoise.log,1
INFO: Loaded existing Interconnect file 'F:/wenjian/第十一章/CCT布线/interconn.iml'
INFO: Loaded existing Interconnect file 'D:/Cadence/SPB_16.2/share/pcb/signal/cds_interconn.iml'
INFO: Finished loading
monitor.sts
#Allegro PCB Router V15.7 made 2006/05/31 at 22:07:34
#Host
#ROUTING STATUS >
Start Time: Report Time: Wed May 27 09:45:38 2009
Nets =
master.rul
DRC Rules Export File for PCB: E:\修改书稿\protel\09源文件\第六章\master.PcbDoc
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width|Scope=Board|Min
master.rul
DRC Rules Export File for PCB: E:\修改书稿\protel\09源文件\第六章\master\master.PcbDoc
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width|Scope=Bo
signoise.log,1
INFO: Loaded existing Interconnect file 'F:/wenjian/第十一章/CCT布线/interconn.iml'
INFO: Loaded existing Interconnect file 'D:/Cadence/SPB_16.2/share/pcb/signal/cds_interconn.iml'
INFO: Finished loading