代码搜索结果
找到约 9,168 项符合
PCB 的代码
readme.txt
Cadence.Allegro.PCB.v16.0
.install lic-server
.copy license_manager\* to lic-manager installdir
.setup lic-mananger
.install allegro (lic-server port 5280)
.point patcher to
ps7219.c
// PS7219
#include
#define uchar unsigned char
#define uint unsigned int
//*************************************************
// ;PCB板接口定义－－6脚排插
// ;6pin---in 输入
// ;1 vcc
// ;2
loadpcb442.m
function c = loadpcb442()
% LOADPCB442 Loads the data file.
% NAME : pcb442
% COMMENT : Drilling problem (Groetschel/Juenger/Reinelt)
% TYPE : TSP
% DIMENSION : 442
% Source: www.iwr.uni-heidel
012.htm
coolbor工作室——PCB设计（经验文章）——高质量设计
new_diaodu.cpp
#include
#include
#include
#include
#include
typedef struct job //job information PCB
{
double arrive_time, excute_
4 port serial interface.cmp
Component : AXIAL0.4
PCB Library : 4 Port Serial Interface.PcbLib
Date : 2004-7-22
Time : 13:31:58
Dimension : 0.472 x 0.092 sq in
Layer(s) Pads(s) Tracks(s
4 port serial interface.cmp
Component : AXIAL0.4
PCB Library : 4 Port Serial Interface.PcbLib
Date : 2004-7-22
Time : 13:31:58
Dimension : 0.472 x 0.092 sq in
Layer(s) Pads(s) Tracks(s
plcc.cmp
Component : LCC84 - duplicate
PCB Library : PLCC.PcbLib
Date : 2004-7-13
Time : 13:28:49
Dimension : 1.232 x 1.232 sq in
Layer(s) Pads(s) Tracks(s) Fill(s)
bestsave.w
(wiring
# Wiring file created by Allegro PCB Router V15.7 made 2006/05/31 at 22:07:34
(resolution MIL 10000)
# Net AOE
(wire (path TOP 80000 -9750000 250000 -9500000 500000)
(net AOE )
signoise.log,3
WARNING: There are no voltage nets defined in this design.
INFO: Using default signal_icnlibs = [interconn.iml cds_interconn.iml *.iml]
INFO: Loaded existing Interconnect file 'E:/Cadence/PCB图的导入、放置