代码搜索:PCB设计
找到约 10,000 项符合「PCB设计」的源代码
代码结果 10,000
www.eeworm.com/read/284743/8903731
doc 课程设计报告内容.doc
www.eeworm.com/read/284743/8903748
doc 课程设计报告封面.doc
www.eeworm.com/read/284672/8910738
doc vc++程序设计.doc
www.eeworm.com/read/284484/8926282
doc 学生选课系统设计报告.doc
www.eeworm.com/read/284433/8930291
txt c语言程序设计.txt
www.eeworm.com/read/284348/8942363
doc com 组件设计与应用.doc
www.eeworm.com/read/186344/8943216
opt 模快化设计范例.opt
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm {
www.eeworm.com/read/186344/8943837
plg 模快化设计范例.plg
礦ision3 Build Log
Project:
E:\C51p编程\模快化设计范例.uv2
Project File Date: 10/30/2006
Output:
www.eeworm.com/read/186331/8944665
txt 译码器的设计.txt
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port(
sel:in std_logic_vector(2 downto 0);
en:in std_logic;
y:out std_logic_vector(7 downto 0)
www.eeworm.com/read/186331/8944851
txt 编码器的设计.txt
library ieee;
use ieee.std_logic_1164.all;
entity ch4_1_2 is
port(a:in std_logic_vector(7 downto 0);
en:in std_logic;
y:out std_logic_vector(2 downto 0));
end ch4_1_2;
architect