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www.eeworm.com/read/394876/8204563
v memory_sizer_dual_path.v
//----------------------------------------------------------------------------
// Wishbone memory_sizer_dual_path core
//
// This file is part of the "memory_sizer" project.
// http://www.opencores.or
www.eeworm.com/read/193603/8214228
gif jsp_cart_install_path.gif
www.eeworm.com/read/173430/9658648
c get_last_path_component.c
/* vi: set sw=4 ts=4: */
/*
* get_last_path_component implementation for busybox
*
* Copyright (C) 2001 Manuel Novoa III
*
* This program is free software; you can r
www.eeworm.com/read/172784/9690477
c list_path_delays_acc.c
/**********************************************************************
* $list_path_delays example -- C source code using ACC PLI routines
*
* C source to scan through a module and list the min
www.eeworm.com/read/172784/9690487
v list_path_delays_test.v
/**********************************************************************
* $list_path_delays example -- Verilog test bench source code
*
* Verilog test bench to test the $list_path_delays PLI app
www.eeworm.com/read/172784/9690520
log list_path_delays_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
list_path_delays_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 9, 1999 14:19:58
Verilog_XL_Turbo_NT 2.6.9 J
www.eeworm.com/read/171788/9737367
m two_path_fading_qpsk.m
% simulate the BER of a QPSK modulated siganal using two path fading channel
% with sigma = fading_sigma
clear;
N_loop = 10000;
N_sym = 100;
N_bit = 2*N_sym; % 2 bits per symbol
p1 = 0.5;
p2