代码搜索：Numeric
找到约 7,754 项符合「Numeric」的源代码
代码结果 7,754
www.eeworm.com/read/407519/2263202
h ublas.h
// Copyright (C) 2006 Garth N. Wells.
// Licensed under the GNU LGPL Version 2.1.
//
// First added: 2006-
// Last changed: 2006-10-10
#ifndef __UBLAS_H
#define __UBLAS_H
#include
www.eeworm.com/read/376468/2710508
sql unitinfo.sql
create table unitinfo(
unitcode char(6) not null, //医保登记号
name char(60) not null, //单位名称
district char(24) not null, //单位属地
unittype char(24) not null, //单位类型
paypercent numeric(8,2) not null,
www.eeworm.com/read/376006/2717720
h pgtypes_error.h
/* $PostgreSQL: pgsql/src/interfaces/ecpg/include/pgtypes_error.h,v 1.8 2006/08/15 06:40:19 meskes Exp $ */
#define PGTYPES_NUM_OVERFLOW 301
#define PGTYPES_NUM_BAD_NUMERIC 302
#define PGTYPES_NUM_
www.eeworm.com/read/366702/2876205
f90 equiv_constraint_4.f90
! { dg-do run }
! { dg-options "-O0" }
! PR20901 - check that derived/numeric equivalence works with std!=f95.
! Contributed by Joost VandeVondele
TYPE data_type
SEQUENCE
INTEGER :
www.eeworm.com/read/351636/3102308
h vcl_limits.h
// This is vcl/vcl_limits.h
#ifndef vcl_limits_h_
#define vcl_limits_h_
#include "vcl_compiler.h"
#if !VCL_CXX_HAS_HEADER_LIMITS || !VCL_USE_NATIVE_STL || (!VCL_NUMERIC_LIMITS_HAS_INFINITY &
www.eeworm.com/read/154079/5642675
vhd cslt_cntr.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
use IEEE.std_logic_unsigned.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entit
www.eeworm.com/read/154079/5642678
vhd sdrmc_state.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
use IEEE.std_logic_unsigned.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entit
www.eeworm.com/read/154079/5642680
vhd rcd_cntr.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
use IEEE.std_logic_unsigned.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entit
www.eeworm.com/read/154079/5642859
vhd sdrm_t.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
use IEEE.std_logic_unsigned.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entit
www.eeworm.com/read/471796/6882043
vhd list_ch07_05_uart_test.vhd
-- Listing 7.5
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_test is
port(
clk, reset: in std_logic;
btn: std_logic_vector(2 downto 0);
rx: in s