代码搜索:Numeric

找到约 7,754 项符合「Numeric」的源代码

代码结果 7,754
www.eeworm.com/read/471796/6881994

vhd list_ch03_13_led_test.vhd

-- Listing 3.13 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity hex_to_sseg_test is port( clk: in std_logic; sw: in std_logic_vector(7 downto 0);
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vhd list_ch03_20_fp_test.vhd

-- Listing 3.20 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fp_adder_test is port( clk: in std_logic; sw: in std_logic_vector(7 downto 0);
www.eeworm.com/read/471796/6882001

vhd list_ch03_14_smadd.vhd

-- Listing 3.14 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sign_mag_add is generic(N: integer:=4); -- default 4 bits port( a, b: in std_logic_vecto
www.eeworm.com/read/471796/6882007

vhd list_ch16_02_pico_btn.vhd

-- Listing 16.2 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pico_btn is port( clk, reset: in std_logic; sw: in std_logic_vector(7 downto 0);
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vhd list_ch16_04_pico_uart.vhd

--Listing 16.4 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pico_uart is port( clk, reset: in std_logic; sw: in std_logic_vector(7 downto 0);
www.eeworm.com/read/471796/6882011

vhd list_ch12_07_dot_gra.vhd

--Listing 12.7 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bitmap_gen is port( clk, reset: std_logic; btn: std_logic_vector(1 downto 0);
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vhd list_ch12_01_vga_sync.vhd

-- Listing 12.1 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vga_sync is port( clk, reset: in std_logic; hsync, vsync: out std_logic; video_
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vhd list_ch12_05_pong_gra_an.vhd

-- Listing 12.5 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pong_graph_animate is port( clk, reset: std_logic; btn: std_logic_vector(1 downto
www.eeworm.com/read/471796/6882022

vhd list_ch11_06_x_rom_sync.vhd

-- Listing 11.6 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity xilinx_rom_sync_template is port( clk: in std_logic; addr: in std_logic_vector(3 downt
www.eeworm.com/read/471796/6882025

vhd list_ch10_03_sram_test2.vhd

--Listing 10.3 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sram_test is port( clk, reset: in std_logic; sw: in std_logic_vector(7 downto 0);