代码搜索：Models
找到约 5,847 项符合「Models」的源代码
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www.eeworm.com/read/139427/13156667
vhd chapter5_models.vhd
entity PAR_TO_SER is
port(LD,SHCLK: in BIT; PARIN: in BIT_VECTOR(0 to 7);
BUSY: inout BIT := '0'; SO: out BIT);
end PAR_TO_SER;
architecture TWO_PROC of PAR_TO_SER is
signal SH_COMP:
www.eeworm.com/read/139427/13156670
vhd chapter6_models.vhd
use work.funcs.all;
entity REG_SYS is
port(C: in BIT; COM: in BIT_VECTOR(0 to 1);
INP: in BIT_VECTOR(0 to 7));
end REG_SYS;
architecture ALG of REG_SYS is
signal R1,R2: BIT_VECTOR(0 t
www.eeworm.com/read/139427/13156673
vhd chapter3_models.vhd
entity ONES_CNT is
port (A: in BIT_VECTOR(2 downto 0);
C: out BIT_VECTOR(1 downto 0));
------ Truth Table:
---
-----------------------------
---|A2 A1 A0 | C1 C0 |
-------------
www.eeworm.com/read/139427/13156676
vhd chapter7_models.vhd
package TIMING_CONTROL is
type TIMING is (MIN,MAX,TYP,DELTA);
constant TIMING_SEL: TIMING := TYP;
function T_CHOICE(TIMING_SEL: TIMING; TMIN,TMAX,TTYP: TIME)
return TIME;
end TIMING_CON
www.eeworm.com/read/139427/13156684
vhd chapter11_models.vhd
-- image processing package declaration
-- (for BEH_INT and BEH_STRUC libraries)
library IEEE;
use ieee.std_logic_1164.all;
---------------- package declaration -----------------------------
www.eeworm.com/read/139427/13156688
vhd chapter1_models.vhd
entity TWO_CONSECUTIVE is
port(CLK,R,X: in BIT;Z: out BIT);
end TWO_CONSECUTIVE;
architecture DATAFLOW of TWO_CONSECUTIVE is
signal Y1,Y0: BIT;
begin
STATE: block((CLK = '1'and not CLK
www.eeworm.com/read/139427/13156691
vhd chapter10_models.vhd
entity DECIMATE is
generic (DEC: INTEGER);
port ( RX,IX: in REAL:=0.0;
N: in REAL:=0.0;
RY,IY: out REAL:=0.0;);
end DECIMATE;
architecture BEHAVIOR of DECIMATE is
begin
proce
www.eeworm.com/read/325790/13184506
m pfgui_example_models.m
function [objects,names]=pfgui_example_models;
% Sorry, I didn't have enough time to write nice and documented GUI code.
% Toolbox for nonlinear filtering.
% Copyright (C) 2005 Jakob Ros閚
www.eeworm.com/read/321281/13409579
jpg cost231models.jpg
www.eeworm.com/read/141300/5772626
deck digital_models2.deck
Code Model Test: d flip-flop, jk flip-flop, toggle ff, set-reset ff
*
*
*** analysis type ***
.tran .01s 4s
*
*** input sources ***
*
vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) )