代码搜索：Models
找到约 5,847 项符合「Models」的源代码
代码结果 5,847
www.eeworm.com/read/438580/7729716
ps models of co-occurrence.ps
%!PS-Adobe-2.0
%%Creator: dvipsk 5.58f Copyright 1986, 1994 Radical Eye Software
%%Title: tr.dvi
%%Pages: 8
%%PageOrder: Ascend
%%BoundingBox: 0 0 612 792
%%DocumentPaperSizes: Letter
%%EndComments
%D
www.eeworm.com/read/437034/7756455
deck digital_models2.deck
Code Model Test: d flip-flop, jk flip-flop, toggle ff, set-reset ff
*
*
*** analysis type ***
.tran .01s 4s
*
*** input sources ***
*
vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3
www.eeworm.com/read/437034/7756461
deck digital_models3.deck
Code Model Test: d latch, set-reset latch, frequency divider
*
*
*** analysis type ***
.tran .01s 8s
*
*** input sources ***
*
vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) )
www.eeworm.com/read/437034/7756511
deck digital_models4.deck
Code Model Test: State Machine, RAM
*
*
*** analysis type ***
.tran .01s 8s
*
*** input sources ***
*
vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0)
+ (3.
www.eeworm.com/read/437034/7756517
deck digital_models1.deck
Code Model Test: buffer, inverter, and, nand, or, nor, xor, xnor
*
*
*** analysis type ***
.tran .01s 4s
*
*** input sources ***
*
v2 200 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) )
www.eeworm.com/read/139427/13156656
vhd chapter4_models.vhd
entity STATEMENTS is
port(X,Y,Z: in INTEGER; -- Note that entity ports are
B: out INTEGER); -- always signals.
end STATEMENTS;
architecture PROP_DELAY of STATEMENTS is
signal AS:
www.eeworm.com/read/139427/13156658
vhd chapter12_models.vhd
--------------------------------------------------------
-- The entity declaration of synthesis example model.
--------------------------------------------------------
entity SYNEX1 is
port (A,
www.eeworm.com/read/139427/13156661
vhd chapter2_models.vhd
--
-- This example illustrates VHDL
-- constructs that can be translated
-- into an iterative network.
--
entity IPAR is
generic (PROP_DEL:time);
port (
R: in BIT_VECTOR (7 downto 0)
www.eeworm.com/read/139427/13156663
vhd chapter8_models.vhd
-- Device to compare two binary inputs.
--
entity COM is
generic (D:time);
port (N1, N0, M1, M0: in BIT;
GE, LE, E, G, L: out BIT);
end COM;
--Figure 8.2 Entity specification for de
www.eeworm.com/read/139427/13156664
vhd chapter9_models.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package FINC is
function INC(X :STD_logic_VECTOR) return std_logic_VECTOR;
end FINC;
package body FINC is
function INC(X : std_logic_VECTOR) retu