代码搜索：Modeling

找到约 1,801 项符合「Modeling」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/400770/11568681

mpf crc32_d32.mpf

[Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys
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www.eeworm.com/read/153541/12028896

mpf comparators.mpf

[Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys
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www.eeworm.com/read/130423/14194850

mpf conencdjprj.mpf

; ; Copyright Model Technology, a Mentor Graphics Corporation company 2003, ; All rights reserved. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../ver
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www.eeworm.com/read/130423/14194878

mpf keyscanprj.mpf

; ; Copyright Model Technology, a Mentor Graphics Corporation company 2003, ; All rights reserved. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../ver
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www.eeworm.com/read/130423/14194903

mpf asic_book_encoder.mpf

; ; Copyright Model Technology, a Mentor Graphics Corporation company 2003, ; All rights reserved. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../ver
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www.eeworm.com/read/224721/14570783

ini modelsim.ini

[Library] others = E:/Model5_2/win32pe/../modelsim.ini work = work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1 ; Show source line containing error. Default is of
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www.eeworm.com/read/221024/14768972

html http:^^www.cs.ucdavis.edu^faculty^joy.html

Server: Netscape-Communications/1.1 Date: Thursday, 21-Nov-96 20:18:39 GMT Last-modified: Friday, 23-Aug-96 20:35:01 GMT Content-length: 695 Content-type: text/html Kenneth I. Joy
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www.eeworm.com/read/154101/5641985

mpf i2c.mpf

; ; Copyright Model Technology, a Mentor Graphics Corporation company 2003, ; All rights reserved. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog std
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www.eeworm.com/read/393841/8260159

ini modelsim.ini

[Library] others = D:/Program Files/Modeltech_5.3d/win32pe/../modelsim.ini [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1 ; Show source line containing error. Defaul
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www.eeworm.com/read/393840/8260411

ini modelsim.ini

[Library] others = E:/Model5_2/win32pe/../modelsim.ini work = work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1 ; Show source line containing error. Default is of
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