代码搜索：MUX
找到约 9,721 项符合「MUX」的源代码
代码结果 9,721
www.eeworm.com/read/211608/15176678
v mux11x3.v
//**************************************************
//** Revision : 0.1
//** File name : mux11x3.v
//** Module name : mux11x3
//** Discription :
//** Simulator : Max+plus II
//** Syn
www.eeworm.com/read/140180/5793515
h streamdata.h
/*****************************************************************************
* streamdata.h: streaming/transcoding data
****************************************************************************
www.eeworm.com/read/288572/8621457
plg mux.plg
Build Log
--------------------Configuration: mux - Win32 Debug--------------------
Command Lines
Creating temporary file "C:\DOCUME~1\ADMINI~1\
www.eeworm.com/read/288572/8621593
ncb mux.ncb
www.eeworm.com/read/288572/8621648
dsp mux.dsp
# Microsoft Developer Studio Project File - Name="mux" - Package Owner=
# Microsoft Developer Studio Generated Build File, Format Version 6.00
# ** DO NOT EDIT **
# TARGTYPE "Win32 (x86) Appli
www.eeworm.com/read/288572/8621696
dsw mux.dsw
Microsoft Developer Studio Workspace File, Format Version 6.00
# WARNING: DO NOT EDIT OR DELETE THIS WORKSPACE FILE!
###############################################################################
www.eeworm.com/read/286532/8760788
bsf mux.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/286532/8760877
vhd mux.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX IS
PORT(
CS : IN STD_LOGIC;
Addr: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
A1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
A2 : IN STD_LOGIC
www.eeworm.com/read/429004/8824752
v mux_if.v
module mux_if(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
always @(in0 or in1 or in2 or in3 or sel)
begin
if(sel==2'b00) out=in0;
else if(sel==2
www.eeworm.com/read/384201/8891021
v mux_if.v
module mux_if(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
always @(in0 or in1 or in2 or in3 or sel)
begin
if(sel==2'b00) out=in0;
else if(sel==2