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/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

Field=Description,String,Description,100|Field=Designator,String,Designator,100|Field=Footprint,String,Footprint,100|Field=LibRef,String,LibRef,100|Field=Quantity,String,Quantity,100|ReportField=Proje

Record=TopLevelDocument|FileName=MCU_S.SCHDOC

------------------------------------------------------------ Single Pin Net Report for MCU_S.SCHDOC -- 2009-4-12 -- 10:08:24 ------------------------------------------------------------

Protel Design System Design Rule Check PCB File : \Wu\MCU_51_TWO\mcu_s.PCBDOC Date : 2008-10-22 Time : 21:12:05 Processing Rule : Hole Size Constraint (Min=0mm) (Max=5mm) (All) Rule Vio

[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath= ChannelDesignatorFormatString=$Component_$RoomName ChannelRoomLevelSeperator=_ OpenOutputs=1 ArchiveProject=0 Timesta