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Thu May 24 10:13:11 2007

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

/*单片机与FPGA端口定义 AD0------P142 A15----------P27 AD1------P141 A14----------P26 AD2------P143 A13----------P11 AD3------P1 A12----------P6 AD4------P2 A11

-- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 pt

Version 7.1 Build 156 04/30/2007 SJ Full Version 36 2035 OFF OFF OFF OFF ON ON OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Pat