代码搜索：Loop
找到约 10,000 项符合「Loop」的源代码
代码结果 10,000
www.eeworm.com/read/412167/11212749
asm prog47a.asm
; PROG47 - Working through the Electronic Breakout Box
;
; Simple Test of the LCD.
;
; This Application waits for 30 msecs and then puts "Hello" onto the LCD's
; Screen.
;
; Myke
www.eeworm.com/read/412167/11212751
asm prog47b.asm
; PROG47 - Working through the Electronic Breakout Box
;
; Simple Test of the LCD.
;
; This Application waits for 30 msecs and then puts "Hello" onto the LCD's
; Screen.
;
; Myke
www.eeworm.com/read/412167/11212754
asm prog47g.asm
; PROG47G - Working through the Electronic Breakout Box
;
;
; Start Taking User Input.
;
; PROG47G - Start Taking Serial Input/Displaying it on the LCD.
;
; PROG47F - Get and Set the Da
www.eeworm.com/read/411123/11255177
lst shijian.lst
A51 MACRO ASSEMBLER SHIJIAN 01/28/2009 22:46:37 PAGE 1
MACRO ASSEMBLER A51 V8.00d
OBJECT MODULE PLACED IN SHIJIAN.OBJ
ASSEMBLER
www.eeworm.com/read/410993/11261476
c main.c
/******************************************************************************
; Lattice Wave Digital Filter to perform Band-pass filtering
;
; Description: This code calls a Lattice Wave Digi
www.eeworm.com/read/147730/12534513
txt 单灯振荡器ddzdq.txt
loop:setb p1.0;
lcall delay;
clr p1.0 ;
lcall delay;
ajmp loop;
delay:mov r7,#250;
d1:mov r6,#250;
d2:djnz r6,d2;
djnz r7,d1;
ret;
end
www.eeworm.com/read/147730/12534609
asm zdq.asm
loop:setb p1.0;
lcall delay;
clr p1.0 ;
lcall delay;
ajmp loop;
delay:mov r7,#250;
d1:mov r6,#250;
d2:djnz r6,d2;
djnz r7,d1;
ret;
end
www.eeworm.com/read/147730/12534610
bak zdq.bak
loop:setb p1.0;
lcall delay;
clr p1.0
lcall delay
ajmp loop
delay:mov r7,#250
d1:mov r6,#250
d2:djnz r6,d2
djnz r7,d1
ret
end
www.eeworm.com/read/248846/12538450
bak crt_data.bak
#include "stdio.h"
#include "math.h"
void main(void)
{
unsigned char kuai,unit,loop;
int data_temp,data_temp1;
FILE *fp;
fp=fopen("data.bin","wb");
/*正弦波*/
for(unit=0;unit
www.eeworm.com/read/248277/12586563
vhd mydivider.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mydivider is
port(divident:in std_logic_vector(3 downto 0);
dividor:in std_logic