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--counter3 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity counter3 is port(clk,clr:in std_logic; bcd:out std_logic_vect

--flash library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity flash is port(clk,en:in std_logic; beam:in std_logic_vector(6 downt

-- seealarm, conctrol displaying the alarm modle Library IEEE; use IEEE.std_logic_1164.all; entity seealarm is port(en:in std_logic; norm:in std_logic_vector(1 downto 0); q:out s

Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg4_1 is PORT(d:in std_logic_vector(3 downto 0); clk : IN std_logic; q:out std_logic_vector(3 downto 0)); END reg4_1; ARCHITEC

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity key_scan is port(clk,key_pre:in std_logic; row:in std_logic_vector(3 downto 0);

package width is constant N1:integer:=2; constant N2:integer:=16; end width; USE work.width.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_u

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity D_flipflop is port(ri,clk:in std_logic; datain :in std_logic_vector(7 downto 0);

library ieee; use ieee.std_logic_1164.all; entity decoder_3_8 is port(a,b,c,g1,g2a,g2b:in std_logic; y:out std_logic_vector(7 downto 0)); end decoder_3_8; architecture rtl of decoder_3_8

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity jioujiaoyan is port(a:in std_logic_vector(7 downto 0); q:out std_logic); end

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity dff is port(a :in std_logic; b :in std_logic; sel:in std_logic; c:out