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找到约 10,000 项符合
Logic Analyzer 的代码
mux2_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux2_1 is
generic(n:integer:=24);
port(
sel:in bit;
A,B:in std_logic;
Y:out std_logic);
end mux2_1;
a
testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
rxt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity rxt is
port(
mclk_16:in std_logic;--16倍baud
rx:in std_logic;--读，复位，和接收端
data:out std_logic_vector(7 downto
clk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a
csout.vhd
library ieee;
Use ieee.std_logic_1164.all;
Entity csout is
port(data:in std_logic_vector(7 downto 0);
cs:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
end csout;
counter4.vhd
--counter4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter4 is
port(clk,clr:in std_logic;
bcd:out std_logic_vecto
counter3.vhd
--counter3
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter3 is
port(clk,clr:in std_logic;
bcd:out std_logic_vect
flash.vhd
--flash
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity flash is
port(clk,en:in std_logic;
beam:in std_logic_vector(6 downt
seealarm.vhd
-- seealarm, conctrol displaying the alarm modle
Library IEEE;
use IEEE.std_logic_1164.all;
entity seealarm is
port(en:in std_logic;
norm:in std_logic_vector(1 downto 0);
q:out s
counter4.vhd
--counter4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter4 is
port(clk,clr:in std_logic;
bcd:out std_logic_vecto