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addsubc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic U
addsubv.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, overflow flag
-- Project : VHDL Library of Arithmet
subc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic Units
-
subcz.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out, zero flag
-- Project : VHDL Library of Arithme
arith_lib.vhd
-------------------------------------------------------------------------------
-- Title : Library component declarations
-- Project : VHDL Library of Arithmetic Units
----------------------
subc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic Units
-
subcz.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out, zero flag
-- Project : VHDL Library of Arithme
arith_lib.vhd
-------------------------------------------------------------------------------
-- Title : Library component declarations
-- Project : VHDL Library of Arithmetic Units
----------------------
led.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LED IS
PORT(
DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LIANG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY LED;
ARCHITECTU
led.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LED IS
PORT(
DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LIANG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY LED;
ARCHITECTU