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找到约 10,000 项符合
Logic Analyzer 的代码
top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS --顶层设计
PORT ( CLK12MHZ : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
csout.vhd
library ieee;
Use ieee.std_logic_1164.all;
Entity csout is
port(data:in std_logic_vector(7 downto 0);
cs:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
end csout;
rxt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity rxt is
port(
mclk_16:in std_logic;--16倍baud
rx:in std_logic;--读，复位，和接收端
data:out std_logic_vector(7 downto
sdr_sdram.vhd
--#######################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: sdr_sdram()
-- COMPANY: Alte
div248.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div248 is
port(clk:in std_logic;------时钟
div2:out std_logic;-----输出2分频信号
div4:out std_logic;-----输出4分
dds_vhdl.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC; --系统时钟
FWOR
reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC; --系统时钟
FWOR
reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0
moore1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE1 IS
PORT (DATAIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RST:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END MOOR