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Logic Analyzer 的代码
bingxingjiafa.txt
library IEEE;use IEEE.std_logic_1164.all;entity adderN is generic(N : integer := 16); port (a : in std_logic_vector(N downto 1); b : in std_logic_vector(N downto 1); cin
control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
cla.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY cla IS
PORT
(
a : IN STD_LOGIC_VE
mux8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux8 is
port(
a,b,c,d,e,f:in std_logic_vector(3 downto 0);
clk:in std_logi
sdram.vhd
-------------------------------------------------------------------
-- By Fangang
-- 2003/05/30
-- SDRAM controller for C6send
-------------------------------------------------------------------
control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
sel.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sel IS
PORT(clk: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
end sel;
ARCHITECTURE are OF sel
clk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a
mux2_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux2_1 is
generic(n:integer:=24);
port(
sel:in bit;
A,B:in std_logic;
Y:out std_logic);
end mux2_1;
a
testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);