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Logic Analyzer 的代码
l_conversions_p.vhd
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------------------------------
-- File Name: l_conversions_p.vhd
-------------------------
songer.vhd
library ieee;
use ieee.std_logic_1164.all;
entity songer is
port(clk12MHZ:in std_logic;
clk8HZ:in std_logic;
spkout:out std_logic);
end;
architecture one of songer is
component notetabs
por
notetabs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end;
architecture one of note
songer.vhd
library ieee;
use ieee.std_logic_1164.all;
entity songer is
port(clk12MHZ:in std_logic;
clk8HZ:in std_logic;
spkout:out std_logic);
end;
architecture one of songer is
component notetabs
por
notetabs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end;
architecture one of note
sipo.vhd
library ieee;--------8 bits serial input parallel output
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sipo is
port (d_in:in std_logic;
three_spi.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity sig_new is
port(
SCK,SDA,CS : in std_logic;
data : out std_logic_vector(11 downto 0);
i2c_master_top.vhd
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level
decode.vhd
--
-- decode.vhd
--
-- cpu decode of JOP3
--
-- generate control for pc and stack
--
--
-- resources on ACEX1K30-3
--
-- xxx LCs, 42.0 MHz
--
-- todo:
--
--
-- 2001-07-03 extracted
bcfetch.vhd
--
-- bcfetch.vhd
--
-- Java bc fetch and address translation for JVM
--
-- resources on ACEX1K30-3
--
-- bytecode LCs, max ca. xx MHz
--
-- todo:
--
-- 2001-11-16 split from fetch.vhd, re