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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; Entity transceiver is port (clk,rst_n,inEn1,inEn2,inEn3 :in std_logic; SPI_SO,FIFO,FIFOP,SFD,CCA :in std_logic;

--===========================================================================-- -- -- S Y N T H E Z I A B L E miniUART C O R E -- -- www.OpenCores.Org - January 2000 -- This core adheres

--===========================================================================-- -- -- S Y N T H E Z I A B L E miniUART C O R E -- -- www.OpenCores.Org - January 2000 -- This core adheres

------------------------------------------------------------------------------- -- -- -- X X XXXXXX XXXXXX

library ieee; use ieee.std_logic_1164.all; entity TENNIS is port(bain,bbin,clr,clk,souclk:in std_logic; ballout:out std_logic_vector(7 downto 0); countah,countal,countbh,countbl:out std_logic_v

-- -- Simple RAM and ROM models -- -- Written by Jiri Gaisler, ESA/ESTEC, 1996 -- library ieee; use ieee.std_logic_1164.all; use ieee.STD_LOGIC_ARITH.all; use std.textio.all; entity FLASHP

-- -- Copyright (C) 1988-1999 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any ot

--控制器协议层 --file :usbf_pd.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity usb_pd is --实体声明 generic(

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux2_1 is generic(n:integer:=24); port( sel:in bit; A,B:in std_logic; Y:out std_logic); end mux2_1; a

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity testda is port(clk:in std_logic; data:out std_logic_vector(7 downto 0);