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Logic Analyzer 的代码
mult8_rtl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mult8_rtl IS
GENERIC(datawidth:INTEGER:=8); --乘数的数据宽度
PORT (
clk : IN STD_LOGIC;
clock_top.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY clock_top IS
PORT(clk : IN STD_LOGIC; --全局时钟
keyvalue : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --按键值
alarmreg.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alarmreg IS
PORT(alarmload : IN STD_LOGIC; --并行加载的控制信号
clk : IN STD_LOGIC; --全局时钟
buffertime : IN STD_LOGIC_VECTOR(23
counter.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
PORT(clk : IN STD_LOGIC; --全局时钟
load : IN STD_LOG
and2.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and2 IS
PORT(
aa,bb : IN STD_LOGIC;
yy : OUT STD_LOGIC);
END and2;
ARCHITECTURE behavier OF and2 IS
BEGIN
yy
bidir_bus.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bidir_bus IS
PORT(
a,b : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); --数据,宽度8位
en : IN STD_LOGIC;
and8_use_and2_test.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and8_use_and2_test IS
PORT(
a1,a2,a3,a4,a5,a6,a7,a8 : IN STD_LOGIC;
y : OUT STD_LOGIC);
END and8_use_and2_test;
ARCHITECTURE be
or2.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY or2 IS
PORT(
a,b : IN STD_LOGIC;
y : OUT STD_LOGIC);
END or2;
ARCHITECTURE behavier OF or2 IS
BEGIN
y
not_gate.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY not_gate IS
PORT(
a : IN STD_LOGIC;
y : OUT STD_LOGIC);
END not_gate;
ARCHITECTURE behavier OF not_gate IS
BEGIN
y
disp_buf.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY disp_buf IS
PORT(
clk : IN STD_LOGIC; --全局时钟
ld : IN STD_LOGIC; --同步加载使能
data : IN STD