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找到约 10,000 项符合
Logic Analyzer 的代码
decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity decoder_3_8 is
port(a,b,c,g1,g2a,g2b:in std_logic;
y:out std_logic_vector(7 downto 0));
end decoder_3_8;
architecture rtl of decoder_3_8
jioujiaoyan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jioujiaoyan is
port(a:in std_logic_vector(7 downto 0);
q:out std_logic);
end
dff.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
port(a :in std_logic;
b :in std_logic;
sel:in std_logic;
c:out
addr.vhd
--addr (模块)正弦
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr is
port(
clk:in std_logic;
dout:out std_logic_vector(5 downto 0)
);
end ad
sanjiao.vhd
--sanjiao 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanjiao is
port(
clk :in std_logic;
dout : out std_logic_vector(5 downto 0)
)
updown2.vhd
-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
port(
r_in:in std_logic;
loadpw.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_3_8 is
port(a,b,c,e1,e2,e3:in std_logic;
y:out std_logic_vector(7
rom256x8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;
ENT
decoder_4_16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_4_16 is
port(a1,b1,c1,d1,g2a1,g2b1:in std_logic;
y1,y2:out std_logi