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Logic Analyzer 的代码
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
b3x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b3x8 is
PORT (CPS : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
YO : OUT STD_L
input_output.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
butterfly1.vhd
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:in
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
standalone.vhd
-------------------------------------------------------------------------------
-- Filename: standalone.vhd
--
-- Description: Sample circuit for doing audio standalone
--
-- VHDL-Sta
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
clk_half.vhd
--provide a 12000000Mhz frequency's clock
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY clk_half IS
PORT(
clk : IN STD_LOGIC;
butterfly1.vhd
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:in
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std