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Logic Analyzer 的代码
serial_generatedinstance.vhd
--------------------------------------------------
-- Model : 8051 Behavioral Model,
-- VHDL Entity mc8051.serial.generatedInstance
--
-- Author : Michael Mayer (mrma
wb_slave.vhd
--
-- file: wb_slave.vhd
-- project: VGA/LCD controller
-- author: Richard Herveille
-- rev 1.0 May 10th, 2001
-- rev 1.1 June 3rd, 2001. Changed WISHBONE ADR_I. Addresses are defined as byte-orient
wb_master.vhd
--
-- File wb_master.vhd, WISHBONE MASTER interface (video-memory/clut memory)
-- Project: VGA
-- Author : Richard Herveille
-- rev.: 1.0 May 1st, 2001
-- rev.: 1.1 June 3rd, 2001. Changed addre
dpm.vhd
--
-- File dpm.vhd (dual ported memory)
-- Author : Richard Herveille
-- rev. 0.1 May 17th, 2001 : Initial release
--
-- fifo_dc uses this entity to implement the dual ported RAM of the fifo.
-
result.vhd
-- output of CoreGen module generator
-- $Header: romrVHT.vhd,v 1.3 1998/06/15 16:22:02 tonyw Exp $
-- *****************************************************************
-- Copyright 1997-1998 - Xi
radd16.vhd
-- output of CoreGen module generator
-- $Header: adreVHT.vhd,v 1.3 1998/06/15 17:52:34 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
mux4w8.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
rsub16.vhd
-- output of CoreGen module generator
-- $Header: subreVHT.vhd,v 1.3 1998/06/15 17:53:11 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-1
uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE