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Logic Analyzer 的代码
txunit.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th
memaccesscomppack.vhd
-- *****************************************************************************************
--
-- Version 0.1
-- Modified 24.07.2005
-- Designed by Ruslan Lepetenok
-- *************************
xmemcomppack.vhd
--************************************************************************************************
-- PM/DM memory components declarations for AVR core (Xilinx)
-- Version 0.4
-- Designed by Ruslan
ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan
avr_uc_comppack.vhd
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modif
ocdprogcp2.vhd
--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
--
jtagcomppack.vhd
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.20
uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
selec.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY selec IS
PORT( clk: IN STD_LOGIC;
selo: out STD_LOGIC_VECTOR (1 DOWNTO 0));
END selec;
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