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-- File: sck_logic.vhd -- -- Created: 8-23-00 ALS -- This file generates an internal SCK by dividing the system clock as determined by CLKDIV. -- This internal SCK has a CPHA=1 relationshi

------------------------------------------------------------------------------- -- Serial/Parallel converter, interfacing JTAG chain with FTDI FT245BM -----------------------------------------------

a = [1 2 0 3 4 2 0]; b = [0 2 3 5 4 0 0]; andResult = a & b % AND 笲衡 orResult = a | b % OR 笲衡 notResult = ~a % NOT 笲衡

a = [0 1 2 3]; result1 = all(a) retult2 = any(a) result3 = any(a

a = [1 2 3; 4 5 6]; output = all(a>2)