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Logic Analyzer 的代码
my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
geweidecord.vhd
library ieee;
use ieee.std_logic_1164.all;
entity geweidecord is
port(key0:in std_logic;
key1:in std_logic;
key2:in std_logic;
key3:in std_logic;
ke
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
pwm.vhd
--
-- pwm.vhd
--
-- PWM DA converter
--
--
--
-- 100k
-- ___
-- sdo o--|___|--o----------o uout
-- |
--
memio.vhd
--
-- memio.vhd
--
-- external memory and IO for JOP3
--
-- addr, wr are one cycle earlier than data
-- dout one cycle after read (ior)
--
-- resources on ACEX1K30-3
-- 24 LCs, xx MHz on