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library ieee; use ieee.std_logic_1164.all; package my_pkg is component div1024--1Hz_generator component Port( clk: in std_logic;--from system clock(1024Hz) f1hz : out std_logic);-- 1H

--shiftrne.vhd n-bit left-to-right shift register --with parallel load and enable library ieee ; use ieee.std_logic_1164.all ; entity shiftrne is generic ( n : integer := 7 ) ; port ( r : i

--divider.vhd n-bit divider library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all ; use work.components.all ; entity divider is generic ( n : integer := 7 ) ; port ( c

--shiftlne.vhd n-bitright-to-left shift register --with parallel load and enable library ieee ; use ieee.std_logic_1164.all ; entity shiftlne is generic ( n : integer := 7 ) ; port( r : in s

library ieee; use ieee.std_logic_1164.all; package my_pkg is component div1024--1Hz_generator component Port( clk: in std_logic;--from system clock(1024Hz) f1hz : out std_logic);-- 1H

--shiftrne.vhd n-bit left-to-right shift register --with parallel load and enable library ieee ; use ieee.std_logic_1164.all ; entity shiftrne is generic ( n : integer := 7 ) ; port ( r : i

--divider.vhd n-bit divider library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all ; use work.components.all ; entity divider is generic ( n : integer := 7 ) ; port ( c

--shiftlne.vhd n-bitright-to-left shift register --with parallel load and enable library ieee ; use ieee.std_logic_1164.all ; entity shiftlne is generic ( n : integer := 7 ) ; port( r : in s

----串行输入（高位在前）的二进制数转换成十进制（BCD码），在n个时钟脉冲下转化n个二这十进制数 ----这是4 bits 二进制数转化成十进制(BCD码)的模块，可以级连使用，转化更多的二进制数 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --use ieee.std_log

library ieee; use ieee.std_logic_1164.all; package my_pkg is component div1024--1Hz_generator component Port( clk: in std_logic;--from system clock(1024Hz) f1hz : out std_logic);-- 1H