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Logic Analyzer 的代码
ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepe
digitalsecondwatch.txt
AAB源程序清单：
library ieee;
use ieee.std_logic_1164.all;
entity aab is
port(a, clk, clr: in std_logic;
q: out std_logic);
end aab;
architecture aab_arc of aab is
begin
process(clk)
variable
interfazv1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity interfaz is
port (
clk: in STD_LOGIC;
resetz: in STD_LOGIC;
data: in STD_LOGIC_VECTOR(5 downto 0);
habili
频率计2.txt
频率计
1. 设计一个4位十进制频率计，其测量范围为1MHz。量程分10kHz、100kHz、1MHz、10Mhz四档(最大读数分别为9.999kHz、99.99kHz、999.9kHz、9999khz),量程自动转换规则如下：
(1) 当读数大于9999时，频率计处于超量程状态，下一次测量时，量程自动增大一档。
(2) 当读数小于0999时
dcm_160.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
grfpushwx.vhd
-----------------------------------------------------------------------------
-- Entity: grfpushwx
-- File: grfpushwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU (shared ver
cnt30.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT30 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S3:OUT STD_LOGIC;
LOAD:IN BIT;
Q3