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Classic Timing Analyzer report for clk_8 Wed Oct 22 22:30:52 2008 Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------------

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Extra Info:

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

This archive contains VPR, an FPGA placement and routing tool, and T-VPack, a program to pack LUTs and flip flops into coarser grained logic blocks and convert a netlist from blif format to VPR's .net

Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Extra Info:

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

Classic Timing Analyzer report for adder2 Sun Apr 19 14:33:25 2009 Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version --------------------- ; Table of Contents ; --------------------