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Logic Analyzer 的代码
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
dff89.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff89 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTO
dff15.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff15 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Dout : OUT STD_LOGIC_VECT
dff8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff8 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_V
ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS
equ_pak.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package equ_pak is
subtype l_byte is std_logic_vector(11 downto 0);
type std_togic_2d is array(natural range)of st
count16.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity count16 is
port(clk:in std_logic;
D,C,B,A:out std_logic
);
end count16 ;
architecture behv of count
testbench.vhd
--testbench.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity testbench is
end entity;
architecture one of testbench is
component connect is
port( inclk: in std_
cfft.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : cfft
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@o