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Logic Analyzer 的代码
frm_logic.frm
VERSION 5.00
Object = "{831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0"; "MSCOMCTL.OCX"
Object = "{67397AA1-7FB1-11D0-B148-00A0C922E820}#6.0#0"; "MSADODC.OCX"
Begin VB.Form frm_load
Caption
sck_logic.vhd
-- File: sck_logic.vhd
--
-- Created: 8-23-00 ALS
-- This file generates an internal SCK by dividing the system clock as determined by CLKDIV.
-- This internal SCK has a CPHA=1 relationshi
61_logic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY
jtag_logic.vhd
-------------------------------------------------------------------------------
-- Serial/Parallel converter, interfacing JTAG chain with FTDI FT245BM
-----------------------------------------------
61_logic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY