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Logic Analyzer 的代码
nco.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
addern8.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity addern8 Is
GENERIC(datawidth:Integer:=8);
port(
cin : in std_logic;
a: in std_logic_vector(datawidth-1
mux3_8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux3_8 is PORT(
a, b, c, d,e,f,g,h: IN STD_LOGIC; --输入8路。
s: IN STD_LOGIC_VECTOR(2 DOWNTO 0); --地址信号
and8.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and8 IS
PORT(
a1,a2,a3,a4,a5,a6,a7,a8 : IN STD_LOGIC;
y : OUT STD_LOGIC);
END and8;
ARCHITECTURE behavier OF and8 IS
BEGIN
y
freqdetect_top.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY freqdetect_top IS
PORT(clk : IN STD_LOGIC; --clk时钟
sign : IN STD_LOGIC; --待测信
ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS
pkg_prims.vhd
--
-- Risc5x
-- www.OpenCores.Org - November 2001
--
--
-- This library is free software; you can distribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as pu
rs232_send.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rs232_send is
port (clk,load,reset:in std_logic;
datain: in std_logic_vector(7 downto 0);
jiafaqimiaoshu.txt
加法器描述
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder