代码搜索结果
找到约 10,000 项符合
Logic Analyzer 的代码
uc_interface.vhd
-- File: uC_interface.vhd
--
-- Author: Jennifer Jenkins
-- Philips Semiconductor
-- Purpose: Description of an interface with a ucontroller/uprocessor
-- (i.e. Motorola 68000)
fir321.cmp
-- Generated by FIR Compiler 3.2.1 [Altera, IP Toolbench v1.2.7 build38]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-
cfft.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : cfft
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@o
serparser.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
juntos.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
cpu.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:16 01/04/2008
-- Design Name:
-- Module Name: CPU - Beha
txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;