代码搜索:Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
www.eeworm.com/read/173695/9641399

vhd reg_e.vhd

---------------------------------------------------------------------- ---- ---- ---- reg_e.vhd
www.eeworm.com/read/173695/9641433

vhd interleaver_e.vhd

---------------------------------------------------------------------- ---- ---- ---- interleaver_e.vhd
www.eeworm.com/read/173695/9641456

vhd delayer_e.vhd

---------------------------------------------------------------------- ---- ---- ---- delayer_e.vhd
www.eeworm.com/read/173672/9643792

vhd comcoun.vhd

--comcoun.vhd 7 segment com scan counter library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity comcoun is port( clk : in std_logic;--synchronouse clock f1k
www.eeworm.com/read/369459/9647672

vhd cnt10.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 is port (clk,rst,en:in std_logic; cq: out std_logic_vector(3 downto 0); cout:out std_logic); end cnt10;
www.eeworm.com/read/369385/9651147

vhd cntm100v.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; -------------------- ENTITY cntm100v IS PORT(en: IN std_logic; clr:in std_logic; clk:in
www.eeworm.com/read/369385/9651175

vhd cntm24v.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; -------------------- ENTITY cntm24v IS PORT(en: IN std_logic; clr:in std_logic; clk:in s
www.eeworm.com/read/369385/9651475

vhd cntm60v.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; -------------------- ENTITY cntm60v IS PORT(en: IN std_logic; clr:in std_logic; clk:in
www.eeworm.com/read/369385/9651579

vhd cntm100v.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; -------------------- ENTITY cntm100v IS PORT(en: IN std_logic; clr:in std_logic; clk:in
www.eeworm.com/read/369385/9651862

vhd cntm24v.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; -------------------- ENTITY cntm24v IS PORT(en: IN std_logic; clr:in std_logic; clk:in s