代码搜索:Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
www.eeworm.com/read/130063/14209760

vhd mc8051_siu_.vhd

------------------------------------------------------------------------------- -- -- -- X X XXXXXX XXXXXX
www.eeworm.com/read/129810/14225505

vhd counter60.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity counter60 is port( clk,clr:in std_logic; low,high:out std_logic_vector(3 dow
www.eeworm.com/read/129810/14225571

vhd counter24.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity counter24 is port( clk,clr:in std_logic; low,high:out std_logic_vector(3 dow
www.eeworm.com/read/231408/14236820

txt 程序代码.txt

--可以数控占空比的(带异步复位)(1M) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PULSE IS PORT(CLK:IN STD_LOGIC; --1M时钟
www.eeworm.com/read/129419/14243345

txt zlgz.txt

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for ins
www.eeworm.com/read/231087/14256816

vhd xspfpga.vhd

-------------------------------------------------------------------------------- -- Copyright (c) 2000 by Trenz Electronic. -- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de --
www.eeworm.com/read/230245/14295585

vhd pulse.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY pulse IS PORT ( clk :IN STD_LOGIC; d:IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; fout:OUT STD_LOGIC); E
www.eeworm.com/read/230245/14295697

bak pulse.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY pulse IS PORT ( clk :IN STD_LOGIC; d:IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; fout:OUT STD_LOGIC;) E
www.eeworm.com/read/229368/14343336

txt abc.txt

2.4.1CPLD 与单片机双向串行通信原理 单片机到CPLD的串行通信接口电路是利用VHDL语言在CPLD中设计一 个串行输入并行输出的八位移位寄存器,其端口与单片机P1.4~P1.7 相连。如 图2-12 所示。CS 为单片机片选信号,当其为低时使能八位寄存器;当CPLD 发出READEY 信号有效CLK1 信号的上升沿到达DCLK 端口时,八位移位寄 存器就会将单片机输出到ram ...
www.eeworm.com/read/228966/14356743

vhd xspfpga.vhd

-------------------------------------------------------------------------------- -- Copyright (c) 2000 by Trenz Electronic. -- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de --