代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/145059/12754614
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/145059/12754626
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/145059/12754643
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/332475/12755792
vhd cpremoveimag.vhd
-- ================================================================================
-- File: CPRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.26.2006
-- Description:
-- This CP
www.eeworm.com/read/332475/12755822
vhd cpremovereal.vhd
-- ================================================================================
-- File: CPRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.26.2006
-- Description:
-- This CP
www.eeworm.com/read/332475/12755851
vhd cpremove.vhd
-- ================================================================================
-- File: CPRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.26.2006
-- Description:
-- This CP
www.eeworm.com/read/332475/12755923
vhd zeroremove.vhd
-- ================================================================================
-- File: ZeroRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.29.2006
-- Description:
-- Zero R
www.eeworm.com/read/332475/12756091
vhd outputbuffer.vhd
-- ================================================================================
-- File: OutputBuffer.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.30.2006
-- Description:
-- Outp
www.eeworm.com/read/332405/12759663
vhd sdrm_timing_tb.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use std.textio.all;
library unisim;
use unisim.vcomponents.all;
USE work.ihdlutil.all;
USE work.vrlgutil.all;
USE std.textio.
www.eeworm.com/read/332405/12759763
vhd sdrm_functional_tb.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use std.textio.all;
library unisim;
use unisim.vcomponents.all;
USE work.ihdlutil.all;
USE work.vrlgutil.all;
USE std.textio.a