代码搜索：LcD
找到约 10,000 项符合「LcD」的源代码
代码结果 10,000
www.eeworm.com/read/453029/1644324
sym lcd.sym
VERSION 5
BEGIN SYMBOL lcd
SYMBOLTYPE BLOCK
TIMESTAMP 2006 2 21 7 43 12
SYMATTR VeriModel "lcd"
SYMPIN 0 -224 Input clk
SYMPIN 0 -32 Input rst
SYMPIN 384 -224 Output lcd_e
SYMPIN 384 -160 Outp
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spl lcd.spl
[Inputs]
clk
rst
[Outputs]
lcd_e
lcd_rw
lcd_rs
=data[7:0]=
[BiDir]
[ATTRIBUTES]
VeriModel lcd
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lfp lcd.lfp
# begin LFP file E:\temp\95144\vhdl\lcd1602\lcd.lfp
designfile lcd.vhd
parttype xc95144xl-tq144-10
bus_delimiter 0;
set_busdelim_onsave 0;
IO_GROUP "data" IO_GROUP="lcd" ;
INST "lcd" COLOR=15 ;
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drc lcd.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net tc_clkcnt is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-
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syr lcd.syr
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.59 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set
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ucf lcd.ucf
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "p18" ;
NET "data" LOC = "p140" ;
NET "data" LOC = "p139" ;
NET "data" LOC
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gyd lcd.gyd
Pin Freeze File: version H.42
95144XL144TQ XC95144XL-10-TQ144
Reset S:PIN71
clk S:PIN128
data S:PIN106
data S:PIN115
data S:PIN111
data S:PIN116
data S:PIN107
data S:PIN1