代码搜索：Lab
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lst lab3.lst
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mptags lab3.mptags
!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.n
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asm lab3.asm
;
; EX0601.ASM
;
LIST P=16F877, R=DEC
#INCLUDE P16F877.INC
CBLOCK 0X20
ENDC
;
; define RAMs
;
ORG 0
NOP
BANKSEL TRISB
MOVLW 0
MOVWF TRISB
MOVWF PORTD
BANKSEL PORTB
MOVLW H
www.eeworm.com/read/177212/9465049
h lab_parameter.h
#ifndef __TG0014_H__
#define __TG0014_H__
// write your header here
//////////////////////////////////
#define DG_CLS_ERASE 0 //(default)
#define DG_CLS_FILL 1 //Parameters of FG_ClearScreen
//////
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mpf lab3.mpf
;
; Copyright Model Technology, a Mentor Graphics Corporation company 2003,
; All rights reserved.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../ver
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vhd lab3.vhd
library ieee ;
use ieee.std_logic_1164.all;
entity shift_register is
port(Clk,Rst,Enable: in std_logic;
Data_in: in std_logic_vector(7 downto 0);
Addr: in std_logic_vector(3 do
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mpf lab4.mpf
; Copyright 2006 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR IT
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qpf lab4.qpf
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
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vhd lab4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity lab4 is
port(
rin :in std_logic_vector(10 downto 1);
sseg1,sseg2:out std_logic_vector(6 downto 0)
);
end lab4;
architect
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pin lab4.pin
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a