代码搜索结果

.code .align 4 s: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r30,12(%r4) ldil L'L$0007,%r19 ldo R'L$0007(%r19),%r19

% { dg-do assemble { target mmix-*-* } } # Base-plus-offset without -linker-allocated-gregs. a TETRA 42 LDO $43,a+52 % { dg-error "no suitable GREG definition" "" } LOC @+256 d TETRA 28 LDO

#as: --no-predefined-syms #objdump: -dr .*: file format elf64-mmix Disassembly of section \.text: 0000000000000000 : 0: 0000002a trap 0,0,42 4: 8d2b0034 ldo \$43,\$0,52 6: R_MMIX_

#objdump: -dr .*: file format elf64-mmix Disassembly of section \.text: 0+ : 0: 0000002a trap 0,0,42 4: 8d2b0034 ldo \$43,\$0,52 6: R_MMIX_REG \.MMIX\.reg_contents

% { dg-do assemble { target mmix-*-* } } # Check that base-plus-offset relocs without suitable GREGs are not passed # through (without -linker-allocated-gregs). a TETRA 42 LDO $43,a+52 % { dg-erro

# All-registers, 'T'-type operands; optional third operand is # register or constant. Main LDA X,Y,Z LDT $32,Y,Z LDBU Y,$32,Z LDTU $232,$133,Z LDO X,Y,$73 LDOU $31,Y,$233 LDW X,$38,$212 LDWU $4

# Simple base-plus-offset b GREG @ a TETRA 42 LDO $43,a+52

# Auto generated by Project Navigator for Modelsim vlib work vlog J:/eda/Xilinx/verilog/src/glbl.v vlog -work work ALU.V ## You need to generate your own Verilog stimuli vsim -t 1ps +maxdelay

# Use a symbolic register areg, presumably allocated by greg in another file. LDO $12,$32,areg LDO $123,areg,34 LDO areg,$234,56

.space $PRIVATE$ .subspa $GLOBAL$ .export $global$ $global$ .space $TEXT$ .subspa $CODE$ .proc .callinfo ivaaddr nop nop addil L%ivaaddr-$global$,%dp ldo R%ivaaddr-$global$(%r1),%r19 .