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LCD 的代码
lcd.v
module lcd(clk,rst,data_in,lcd_e,lcd_rw,lcd_rs,data);
input clk,rst;
input [7:0] data_in;
output lcd_e,lcd_rw,lcd_rs;
output [7:0] data;
reg lcd_e,lcd_rw,lcd_rs;
reg [7:0] data,data_in_buf
lcd.v
module lcd(clk,rst,data_in,lcd_e,lcd_rw,lcd_rs,data);
input clk,rst;
input [7:0] data_in;
output lcd_e,lcd_rw,lcd_rs;
output [7:0] data;
reg lcd_e,lcd_rw,lcd_rs;
reg [7:0] data,data_in_buf
lcd.sym
VERSION 5
BEGIN SYMBOL lcd
SYMBOLTYPE BLOCK
TIMESTAMP 2006 4 21 13 15 35
SYMATTR VeriModel "lcd"
SYMPIN 0 -224 Input clk
SYMPIN 0 -128 Input rst
SYMPIN 0 -32 Input data_in(7:0)
SYMPIN 384 -224
lcd.spl
[Inputs]
clk
rst
=data_in[7:0]=
[Outputs]
lcd_e
lcd_rw
lcd_rs
=data[7:0]=
[BiDir]
[ATTRIBUTES]
VeriModel lcd