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lcd.ut

-w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp

lcd.pcf

//! ************************************************************************** // Written by: Map H.42 on Tue Feb 07 14:36:15 2006 //! ***************************************************************

lcd.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lcd is Port ( clk : in std_logic; --40MHZ Reset : in std

lcd.prj

vhdl work "char_ram.vhd" vhdl work "lcd.vhd"

lcd.cdf

/* Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EPM1270T144) Path("") File("lcd.pof")

lcd.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

lcd.done

Tue Jul 10 15:36:25 2007

lcd.qws

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 [P