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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity char_ram is port( address : in std_logic_vector(5 downto 0) ; data : out std_logic_vector(7 downto 0) );

.i 4 .o 11 .s 8 .p 20 .reset Rst .resettype async .clock Clk .resetstate st0 .type fdr .ilb In0 In1 In2 In3 .ob Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Out8 Out9 Out10 .obdefault 00000

.i 4 .o 11 .s 8 .p 20 .reset Rst .resettype async .clock Clk .resetstate st0 .type fdr .ilb In0 In1 In2 In3 .ob Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Out8 Out9 Out10 .obdefault 00000

.i 4 .o 11 .s 8 .p 20 .reset Rst .resettype async .clock Clk .resetstate st0 .type fdr .ilb In0 In1 In2 In3 .ob Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Out8 Out9 Out10 .obdefault 00000

.i 4 .o 11 .s 8 .p 20 .reset Rst .resettype async .clock Clk .resetstate st0 .type fdr .ilb In0 In1 In2 In3 .ob Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Out8 Out9 Out10 .obdefault 00000

# XST flow : Creating project file lcd.prj # xst flow : RunXST lcd.prj __projnav/lcd.xst ./xst # XST flow : Creating project file lcd.prj # xst flow : RunXST lcd.prj __projnav/lcd.xst ./xst

set allSynthModules {char_ram.MOD lcd.MOD}

.i 4 .o 11 .s 8 .p 20 .reset Rst .resettype async .clock Clk .resetstate st0 .type fdr .ilb In0 In1 In2 In3 .ob Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Out8 Out9 Out10 .obdefault 00000

set ADucfFile {lcd.ucf}

# XST (Creating Lso File) : lcd.lso # xst flow : RunXST lcd.syr lcd.prj lcd.sprj lcd.ana lcd.stx lcd.cmd_log lcd.ngc lcd.ngr # Implmentation : Translate (CPLD flow) __projnav/lcd_edfTOngd