代码搜索：Key1
找到约 1,573 项符合「Key1」的源代码
代码结果 1,573
www.eeworm.com/read/299942/7819540
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/491206/6441758
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/478253/6722733
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/402018/11544004
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/339668/12210782
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/211745/15174643
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/14792/410875
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/15064/430721
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/17540/737575
cpld
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/17609/742744
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec